1. Field of the Invention
The present invention relates to the manufacturing of a bipolar transistor in a BICMOS integrated circuit manufacturing technology incorporating, in particular, bipolar components and complementary MOS (CMOS) components.
The present invention more specifically relates to such a technology in which the dimensions of an clement patterned on a mask may be lower than or equal to 0.4 xcexcm, for example, from 0.2 to 0.35 xcexcm.
2. Discussion of the Related Art
A BICMOS-type technology to which the present invention applies is described in French patent numbers No96/14408, No96/14409, No96/14410, No96/14411, No96/14412, all filed Nov. 19, 1996, number No96/16065, filed Dec. 20, 1996, number No96/16337, filed Dec. 27, 1996, and number No98/01313, filed Jan. 30, 1998. All of these applications are incorporated herein by reference.
The structure of a bipolar transistor in such a technology will be explained hereafter, in relation with the simplified cross-sectional views of FIGS. 1 to 4.
As illustrated in FIG. 1, the structure is formed in a P-type substrate 1 including a buried layer 2 of type N+ over which is formed an N-type lightly-doped epitaxied layer 3. An active area is delimited by an oxide region 4. Above the active area, a P-type doped polysilicon layer 6 and a protection oxide layer 7 are successively deposited. Layers 6 and 7 are altogether opened at the level of the central portion of the active area. It should be noted that, upon etching of layers 6 and 7, the apparent upper surface of epitaxial layer 3 is inevitably slightly dug in. After this, a thermal oxidation is performed to form a thin oxide layer 8, having for example a thickness of approximately 5 nm on the sides of polysilicon layer 6 and on the surface of the central area of the epitaxial layer. During this step, the P-type dopants contained in polysilicon 6 diffuse in epitaxial layer 3 to form an extrinsic base region 10. Then, a P-type dopant, for example, boron, is implanted, the implanted area, marked with crosses, being designated with reference 11. Further, prior to the boron implantation, a very high energy N-type implantation is performed to form a lower collector region 12 more heavily doped than epitaxial layer 3.
Conventionally, the collector contact is recovered by an N+-type diffused region, not shown, contacting buried layer 2 and extending up to the surface. This collector structure will not be shown and described in the following description, given that it is a conventional structure.
At the following step, illustrated in FIG. 2, compound spacers are formed. These spacers are formed by depositing a thin silicon nitride layer followed by a polysilicon layer. After anisotropically etching the polysilicon, there only remain polysilicon spacers 14. After this, the silicon nitride is etched and there only remain portions of silicon nitride 15 under the polysilicon.
The advantage of forming such compound spacers with respect to the conventional forming of oxide spacers or nitride spacers is that good insulation is obtained, and that it is possible to define very precise dimensions. The width of the compound spacers is essentially determined by the polysilicon thickness. The polysilicon etching is performed by plasma with a stop on the nitride layer which has for example a 30-nm thickness. The nitride etching is performed chemically with a stop on the oxide layer. The selectivity being extremely high, oxides 7 and 8 are not consumed. The etching of the silicon oxide is then performed chemically and induces no silicon consumption. After this step, a heavily-doped N-type polysilicon layer 19 is deposited, this layer being preferably coated with a silicon oxide layer 19. The structure illustrated in FIG. 3 is thus obtained.
Then, a fast thermal anneal is performed, for example, at 1040xc2x0 C. for a duration of 40 s to obtain a diffused structure of the type illustrated in FIG. 4. An emitter region 20 diffused from polysilicon 18 and formed in a P-type base region resulting from the diffusion of implanted area 11 is thus obtained. Considering the base in more detail, it can be divided into three regions, extrinsic base region 10 resulting from the diffusion from P-type doped polysilicon 6, an intrinsic base region 22 under emitter region 20 and an intermediary region 24 between the intrinsic and extrinsic base regions, under the compound spacer.
A priori, intermediary region 24 could have been expected to diffuse like intrinsic region 22 since both regions result from the same implantation 11. In fact, region 24 appears to diffuse much less deeply and thus remains more concentrated. Various reasons may be found to explain this phenomenon most likely to be linked to the presence of silicon nitride spacer 14 above region 24. This could seem favorable since the relatively high doping level of region 24 with respect to region 22 tends to reduce the resistance of access to the base, However, given the very small dimensions of a component according to the present invention, the homogeneous lateral extent of region 24 is in practice on the order of 50 to 80 nm only and its resistance is anyway small compared to that of the other stray resistive elements of the structure. Conversely, the fact that a region of greater doping density is located in the vicinity of the edge of junction 20 tends to deteriorate the forward current-voltage characteristics of the base-emitter junction, and thus to reduce the transistor gain.
An object of the present invention is to provide a modified method of manufacturing improving the characteristics of the emitter-base junction of a bipolar transistor.
Another object of the present invention is to provide such a modified method which does not increase the number of masking and etching steps with respect to the prior art method.
To achieve these and other objects, the present invention provides a method of manufacturing the base and emitter regions of a bipolar transistor in an active area of a first conductivity type, including the steps of depositing a first heavily-doped polysilicon layer of the second conductivity type; eliminating the first polysilicon layer in its central portion; growing a thermal oxide layer; performing an implantation of the second conductivity type at a first dose; forming silicon nitride spacers at the internal periphery of the first polysilicon layer; performing a second implantation of the second conductivity type at a second dose; eliminating the central oxide layer; depositing a second polysilicon layer of the first conductivity type, and performing a fast thermal anneal; in which the second dose is selected to optimize the characteristics of the base-emitter junction and the first dose is smaller than the second dose.
According to an embodiment of the present invention, the first conductivity type is type N and the second conductivity type is type P.
According to an embodiment of the present invention, the first dose results from a boron (B11) implantation and the second dose results from a boron fluoride (BF2) implantation.
According to an embodiment of the present invention, the first implantation is performed at a dose from 0.7 to 1 1013 at./cm2 under a 5 keV energy and the second implantation is performed at a dose on the order of 3 to 5 1013 at./cm2 under a 25 keV energy.
The present invention also provides a bipolar transistor, the base region of which includes a first central portion of a first doping level; a first peripheral portion of a second doping level; a second peripheral portion of a third doping level, in which the second doping level is smaller than the first level, itself smaller than the third level.
According to an embodiment of the present invention, the first peripheral region is arranged under a nitride spacer.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.